module Dig_Driver (
    input wire rst,
    input wire clk,
    input wire [11:0] addr,
    input wire wen,//CPU写地址是写道dig的收，这个wen才会有效
    input wire [31:0] wdata,
    output reg [ 7:0]  dig_en,
    output reg         DN_A,
    output reg        DN_B,
    output reg         DN_C,
    output reg         DN_D,
    output reg        DN_E,
    output reg        DN_F,
    output reg         DN_G,
    output reg         DN_DP  //这个点好像没用到过？
);


wire cnt_end; // 计数结束标志
reg [12:0] cnt;// 计数器，控制dig_en 刷新
reg [7:0] led[15:0];//led显示内容
reg [31:0] disp_data;

assign cnt_end = (cnt == 13'd5000);
assign led_dp = 1;
    
always @ (posedge clk or posedge rst) begin //控制cnt计数器
    if (rst || cnt_end) cnt <= 15'd1;
    else cnt <= cnt + 15'd1;
end

//rst模块
always @ (posedge clk or posedge rst) begin 
    if ( rst) begin
    led[0]  <= 7'b0000001; led[1]  <= 7'b1001111;
    led[2]  <= 7'b0010010; led[3]  <= 7'b0000110;
    led[4]  <= 7'b1001100; led[5]  <= 7'b0100100;
    led[6]  <= 7'b0100000; led[7]  <= 7'b0001111;
    led[8]  <= 7'b0000000; led[9]  <= 7'b0001100;
    led[10] <= 7'b0001000; led[11] <= 7'b1100000;
    led[12] <= 7'b1110010; led[13] <= 7'b1000010;
    led[14] <= 7'b0110000; led[15] <= 7'b0111000;
    end
end

always @ (posedge clk or posedge rst) begin//控制使能信号dig_en
    if (rst) dig_en <= 8'b0111_1111;
    else if (cnt_end) dig_en <= {dig_en[0] , dig_en[7:1]};
end 

always @(posedge clk or posedge rst) begin 
    if (rst) disp_data <= 32'h0;
    else if (wen ) disp_data <= wdata;

end

always @ (posedge clk or posedge rst) begin// 控制数码管
    if (rst) {DN_A,DN_B,DN_C,DN_D,DN_E,DN_F,DN_G} <= 7'b111_1111;
    else begin
        case(dig_en)//根据使能信号控制灯
            8'b0111_1111 : {DN_A,DN_B,DN_C,DN_D,DN_E,DN_F,DN_G} <= led[disp_data[31:28]];
            8'b1011_1111 : {DN_A,DN_B,DN_C,DN_D,DN_E,DN_F,DN_G} <= led[disp_data[27:24]];
            8'b1101_1111 : {DN_A,DN_B,DN_C,DN_D,DN_E,DN_F,DN_G} <= led[disp_data[23:20]];
            8'b1110_1111 : {DN_A,DN_B,DN_C,DN_D,DN_E,DN_F,DN_G} <= led[disp_data[19:16]];
            8'b1111_0111 : {DN_A,DN_B,DN_C,DN_D,DN_E,DN_F,DN_G} <= led[disp_data[15:12]];
            8'b1111_1011 : {DN_A,DN_B,DN_C,DN_D,DN_E,DN_F,DN_G} <= led[disp_data[11:8]];
            8'b1111_1101 : {DN_A,DN_B,DN_C,DN_D,DN_E,DN_F,DN_G} <= led[disp_data[7:4]];
            8'b1111_1110 : {DN_A,DN_B,DN_C,DN_D,DN_E,DN_F,DN_G} <= led[disp_data[3:0]];
        default:{DN_A,DN_B,DN_C,DN_D,DN_E,DN_F,DN_G} <=8'h00;
        endcase
    end
end
    
endmodule